In memory cell arrays, in particular in DRAM arrays, information is stored in the form of electrical charges in the individual memory cells. In many of such cells, the electrical charge is stored in memory capacitors. Here, the charge is retained in the memory capacitor for only a limited time. In DRAM arrays the retention time in a memory capacitor is approximately 2 to 3 seconds. In order to retain the stored information for longer, the information is periodically refreshed.
It has become apparent that individual memory cells in memory cell arrays have fluctuating retention times. Therefore, the retention time in the memory cells fluctuates between very small values, for example 10 milliseconds, and customary retention times of 2 to 3 seconds. This fault, which is also referred to as a variable retention time failure, is not predictable.
It is accordingly an object of the invention to provide a memory cell array and method for fabricating it which overcome the above-mentioned disadvantages of the prior art devices and methods of this general type, in which fluctuations in the retention time of a stored charge are reduced.
With the foregoing and other objects in view there is provided, in accordance with the invention, a memory cell array having memory cells, including: a capacitor electrode formed of a polycrystalline semiconductor material; a monocrystalline semiconductor region forming an electrical connection with the polycrystalline semiconductor material of the capacitor electrode; and islands formed of an amorphous material disposed in an area of the electrical connection between the polycrystalline semiconductor material and the monocrystalline semiconductor region.
In a memory cell array having memory cells in which there is an electrical connection between the polycrystalline semiconductor material of the capacitor electrode and the monocrystalline semiconductor region, islands made of amorphous material are disposed in the vicinity of the electrical connection between the polycrystalline semiconductor material and the monocrystalline semiconductor region. The islands made of amorphous material stabilize the boundary face between the monocrystalline semiconductor region and the polycrystalline semiconductor material of the capacitor electrode. This avoids the situation during the fabrication process, in particular during heat-treatment steps, in which the boundary face between the polycrystalline semiconductor material and the monocrystalline semiconductor region changes in such a way that on the one hand epitaxial growth emanating from the surface of the monocrystalline semiconductor region extends into the polycrystalline semiconductor material, and on the other hand granular growth emanating from the polycrystalline semiconductor material extends into the monocrystalline semiconductor region.
Preferably, the islands are disposed in the vicinity of the electrical connection in a planar configuration in an irregular grid.
The islands may have various shapes. In particular, the islands may be conical, ellipsoidal, rotationally ellipsoidal or of irregular shape. In particular, the various islands may have different shapes.
The invention is based on the following ideas: the variable retention time failure effect is observed in the memory cells in which there is an electrical connection between a monocrystalline semiconductor region and polycrystalline semiconductor material of a capacitor electrode. It is observed in particular in memory cells in which a selection transistor is disposed in a monocrystalline semiconductor substrate, the one source/drain region of the selection transistor is electrically connected to a capacitor electrode which is disposed in a trench and is made of polycrystalline semiconductor material. The variable retention time failure effect also occurs in memory cells with a stacked capacitor.
Investigations have shown that memory cells with a variable retention time failure effect in the monocrystalline semiconductor region exhibit crystal defects which emanate from the boundary face between the monocrystalline semiconductor region and the polycrystalline semiconductor material. The defects are considered to be a consequence of the unstable boundary faces between the polycrystalline semiconductor material and the monocrystalline semiconductor region.
According to the invention, islands made of amorphous material are disposed between the polycrystalline semiconductor material and the monocrystalline semiconductor region. The islands cause mechanical tension both on the surface of the monocrystalline semiconductor region and on the surface of the polycrystalline semiconductor material. In heat-treatment processes, the mechanical tension on the aforesaid surfaces prevents epitaxial growth emanating from the surface of the monocrystalline semiconductor region and granular growth emanating from the polycrystalline semiconductor material. As a result of the granular growth emanating from the polycrystalline semiconductor material, the crystal lattice defect that is present in the polycrystalline semiconductor material is transferred into the monocrystalline semiconductor region. The epitaxial growth emanating from the surface of the monocrystalline semiconductor region into the polycrystalline semiconductor material also brings about defects in the crystal in the monocrystalline semiconductor region. These defects, which may lead inter alia to dislocations, are avoided in the memory cell array according to the invention by the provision of the islands made of amorphous material.
At the same time, the islands made of amorphous material ensure that there is an electrical contact between the polycrystalline semiconductor material and the monocrystalline semiconductor region, since charge carriers can migrate through, between the islands made of amorphous material, from the polycrystalline semiconductor material into the monocrystalline semiconductor region. Furthermore, diffusion of doping material between the polycrystalline semiconductor material and the monocrystalline semiconductor region is possible.
Both insulating material, in particular SiO2 or Si3N4, and conductive material, in particular tungsten or another metal with a high melting point, are suitable for the islands made of amorphous material.
The monocrystalline semiconductor region is in particular part of a semiconductor substrate, which has monocrystalline silicon at least in the vicinity of the electrical connection. A monocrystalline silicon wafer or a monocrystalline silicon layer of an SOI substrate are, inter alia, suitable as a semiconductor substrate.
The islands made of the amorphous material are preferably formed from oxide, in particular from silicon dioxide.
During the fabrication of the memory cell array, an amorphous layer of a predefined thickness is preferably applied to the surface of the monocrystalline semiconductor region in the vicinity of the electrical connection. Polycrystalline semiconductor material is applied on top of this. Here, the amorphous layer ensures that the polycrystalline semiconductor material grows in a polycrystalline fashion. In order to form the islands made of the amorphous material, preferably a heat-treatment step is carried out, during which step the amorphous layer breaks up into the islands.
Such a formation of oxide islands from a previously continuous oxide layer by a heat-treatment process is already known, in conjunction with bipolar transistors, from H. Schaber et al., IEDM 1987, pages 170 to 173. Such a heat-treatment step is used to break up the so-called native oxide layer or layer which arises when the substance is exposed to air and is formed uncontrollably on exposed silicon surfaces. The native oxide layer leads to increased resistance values between the emitter and the emitter connection on the surface of the emitter in bipolar transistors. The thermal breaking up of the layer of oxide that arises when the substance is exposed to air in the case of bipolar transistors improves the emitter resistance. However, there is no reference to the influence of islands made of amorphous material on the occurrence of defects in monocrystalline semiconductor material in H. Schaber et al., IEDM 1987, pages 170 to 173.
The monocrystalline semiconductor region is in particular a source/drain region of a selection transistor. The capacitor electrode is disposed in particular in a trench that is etched into a semiconductor substrate and is part of a so-called trench capacitor which, in addition to the capacitor electrode, has a capacitor dielectric and a part of the semiconductor substrate adjacent to the trench as counterelectrode. The capacitor electrode can also be disposed on the surface of the semiconductor substrate, in which selection transistors are disposed, and can be part of a stacked capacitor.
Preferably, the islands are disposed in such a way that the ratio of a distance between adjacent islands to the diameter of the islands is 10:1 at maximum, preferably between 2:1 and 1:1 at maximum. This configuration ensures that the tensions that are caused by the islands are distributed uniformly over the surface of the monocrystalline semiconductor region in the vicinity of the electrical connection, and thus prevent the formation of defects over the entire area.
Preferably, the islands have dimensions in the range between 0.5 and 50 nm parallel to the surface of the monocrystalline semiconductor region. The distances between adjacent islands are also 0.5 to 50 nm. They have a thickness between 0.5 nm and 15 nm perpendicular to the surface of the monocrystalline semiconductor region. The surface on which the islands are disposed is considered here in each case to be the surface of the monocrystalline semiconductor region. This surface may lie in particular in the upper area of a wall of a trench in which the capacitor electrode is disposed, and may be aligned perpendicular to a main face of a semiconductor substrate.
According to one preferred embodiment, the islands have dimensions in the range between 8 and 20 nm parallel to the surface of the monocrystalline semiconductor region. The distances between adjacent islands are approximately 12 nm. They have a thickness of approximately 8 nm perpendicular to the surface of the monocrystalline semiconductor region.
During the manufacture of the memory cell array, the amorphous layer is preferably formed by thermal oxidation. In order to ensure the controlled fabrication of the amorphous layer to a predefined thickness, a predefined temperature and time is maintained here in an oxidizing atmosphere. The oxidizing atmosphere here can be achieved by oxygen in a residual gas, oxygen in the atmosphere, in particular in air, or by a selectively added reaction gas with oxygen. In terms of the controllability of the thickness of the amorphous layer, it is advantageous here to carry out the thermal oxidization at a relatively low temperature, in particular in the range between 500 and 625xc2x0 C.
The heat treatment to form the islands is preferably carried out in the range between 950 and 1150xc2x0 C. Here, use is made of the fact that islands whose diameters and spacing can be predefined by the thickness of the amorphous layer are formed spontaneously at such high temperatures.
The islands made of amorphous material can be formed in another way, for example by depositing an amorphous layer that is structured with the aid of a statistically formed mask or with the aid of electron beam lithography.
Other features which are considered as characteristic for the invention are set forth in the appended claims.
Although the invention is illustrated and described herein as embodied in a memory cell array and method for fabricating it, it is nevertheless not intended to be limited to the details shown, since various modifications and structural changes may be made therein without departing from the spirit of the invention and within the scope and range of equivalents of the claims.
The construction and method of operation of the invention, however, together with additional objects and advantages thereof will be best understood from the following description of specific embodiments when read in connection with the accompanying drawings.